Saurabh S. Agrawal



EMAIL :

saurabh.jvl15@ee.iitd.ac.in
saurabh.sa27@gmail.com


AREAS OF INTEREST :

Physical Design, STA, Digital Circuit/RTL Design, ASIC/SoC Design, Mixed Signal VLSI Design


SPONSOR : Internal Project


 


ABOUT ME :

I am from Washim, Maharashtra. I obtained my Diploma in Electronics & Communication from Government Polytechnic, Washim and completed my Bachelor's degree in Electronics & Telecommunication from Maharashtra Institute of Technology, Pune. Prof. M. Balakrishnan is my M.Tech supervisor at IIT Delhi.


MY COURSES :

System Level Design and Modeling, Synthesis of Digital systems, Analog Integrated circuits, MOS VLSI Design, Architecture and Algorithm for DSP Systems, Mixed Signal Circuits, Semiconductor Memory Design, Digital System Design, Physical Design